1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device to which a plurality of integrated circuits such as, microprocessors, logic circuits and the like are connected in series.
2. Description of the Related Art
Recently, the degree of integration of an integrated circuit device has been significantly improved, and in a semiconductor memory of a giga (G) bit order, several hundred million elements are integrated in one chip. In a 64-bit microprocessor, several million to ten million elements are integrated in one chip. The improvement of the degree of the integration is achieved by downsizing the elements. In the case of a 1 G-bit DRAM (dynamic random access memory), MOS (metal oxide semiconductor) transistors having a gate length of 0.15 .mu.m are used, and for a higher degree of integration, MOS transistors having a gate length of 0.1 .mu.m or less are used.
In a MOS transistor of such a small size, deterioration of transistor characteristics occurs because of the generation of a hot carrier, or breakdown of insulation films occurs because of the TDDB (time dependent dielectric breakdown). Further, in the case where the concentration of impurities in a bulk or a channel portion is raised in order to suppress a decrease in threshold voltage caused by shortening of the channel length, the junction breakdown voltage between a source and a drain, is decreased.
In order to maintain the reliability of these fine elements, it is effective to decrease the supply voltage. More specifically, the generation of a hot carrier is avoided by weakening the electric field running in the lateral direction between the source and drain, and the TDDB is prevented by weakening the electric field running in the vertical direction between the gate and bulk. Further, by decreasing the supply voltage, a reverse bias acting on the junction between the source and the bulk or between the drain and the bulk, is decreased, thus making it possible to follow up a decrease in the junction breakdown voltage.
In the meantime, in a bipolar transistor, a high-speed operation can be achieved by shortening the base width; however if the base width is excessively shortened, the bipolar transistor cannot function as a transistor because of punch through. In order to avoid this, it is necessary to increase the concentration of impurities in the base. Further, if the current density is increased, the cutoff frequency is decreased. In order to avoid this so-called Kirk effect (or base pushout effect), it is necessary to increase the concentration of impurities in the collector.
In the downsized bipolar transistor, the concentration of the impurities in the base and the collector region must be increased, and with an increase in the concentration, the base-collector junction breakdown voltage is decreased. In order to avoid this, a decrease in the supply voltage is effective as in the case of the MOS transistor.
As described above, in the case where elements are downsized, it is necessary to decrease the supply voltage in order to maintain the reliability of the device; however, at the same time, the structure of the device is complicated for a user who actually deals with the semiconductor integrated circuit device (semiconductor chip), creating a problem. In other words, for a user, it is not preferable that the supply voltage should differ from one chip to another among a plurality of semiconductor chips. Further, it is not preferable that the supply voltage which has been used in the conventional structure should become unusable as it is.
Recently, a device as shown in FIG. 1, in which the supply voltage is decreased within a semiconductor chip, has been proposed. In this device, a voltage down converter 111 and an integrated circuit 110 are connected in series between a power line (supply voltage Vcc) and a ground line (ground voltage Vss), thus maintaining the voltage applied to the integrated circuit 110 at Vcc' which is lower than Vcc. With use of the voltage down converter 111, the reliability of the semiconductor chip is increased.
However, in a device of the above-described type, the power consumed in the voltage down converter 111 is wastefully used. Therefore, it is difficult to achieve a power-saving performance of the semiconductor chip as a whole, creating a new problem. For example, in the case where supply voltage Vcc=3 V and the voltage applied to the integrated circuit 110 is 1.5 V, a subtracted voltage difference of 1.5 V is applied to the voltage down converter 111, and thus a half of the total consumption power is used in the voltage down converter 111.
More specifically, the consumption power P of a semiconductor chip as a whole is expressed by P=CV.sup.2 f, where V indicates the difference between the supply voltage and the ground voltage, C indicates the capacitance between the power sources of the semiconductor chip, and f indicates the operation frequency. In FIG. 1, if the capacitance between the power sources of the voltage down converter 111 and the capacitance between the power sources of the integrated circuit 110 are both equal to C1, an equation, Vcc'=Vcc/2, is established. Therefore, the power consumed in the semiconductor chip as a whole is (C1)V.sup.2 f and the power consumed in the voltage down converter 111 is (C1/2)V.sup.2 f. Thus, one half of the consumption power of the semiconductor chip as a whole is consumed by the voltage down converter 111.
For the purpose of suppressing the consumption of the power in a voltage down converter, the following device has been proposed (Jap. Pat. Appln. KOKAI Publication No. H4-3153131). According to this technique, two integrated circuits are connected in series between the power line and the ground line, and the current flowing through the first integrated circuit is recycled in the second integrated circuit. Further, a voltage control circuit is connected to a power line within the semiconductor chip, which is a connection portion between the first and second integrated circuits, so as to maintain a voltage of the power line in the chip at constant.
In this device, however, if the first and second integrated circuits do not function at the same time, the load on the voltage control circuit is increased. Therefore, a voltage control circuit having a drive capability as large as that of the voltage down converter is required. As a result, the consumption power cannot be decreased.
As described above, conventionally, in a semiconductor integrated circuit device employing fine elements, a voltage down converter is used in order to maintain the reliability of the device and to avoid the complexity of the structure; however, the power consumed in such a voltage down converter is wasted.
Meanwhile, in a device in which a plurality of integrated circuits are connected in series without using a voltage down converter, the drive capability of the internal voltage control circuit must be enhanced when these integrated circuits are not operated at the same time. As a result, the power substantially the same as that consumed in a voltage down converter when the voltage down converter is used, is consumed by the voltage control circuit, and such power is wastefully used.